8-6

MS622424

MOSEL VITELIC

MS622424 Rev. 1.0 January 1995

Pin Descriptions

Pin Name

Description

PIXIN0–PIXIN23

These inputs are latched on the rising edge of CLOCK.IN. The PIXIN0–PIXIN23

can be utilized in two different modes. In the Color Index Mode, PIXIN0–PIXIN12

are used to look up a 24 bit color from a palette of 8192 colors; the higher order

bits in this mode are ignored.

In the RGB Mode, PIXIN0–PIXIN7, PIXIN8–PIXIN15, and PIXIN16–PIXIN23 will

address a red, green, or blue color value, respectively, from the 8K color palette.

Internally, the five higher order bits are appended to the 8-bit addresses to

compose the necessary 13 bits to address 8K locations. The five appended bits

can be one of three values:(1)11101, (2)11110, or (3)11111.

These binary addresses are expressed with the most significant bit on the left. The

RGB Mode and five higher order bits are determined by the values of PIX.RGB0

and PIX.RGB1.

PIX.RGB0–PIX.RGB1

These two input pins select Color Index Mode or RGB mode. The table below

defines the selection associated with the values of these two bits.

PIX.RGB1 PIX.RGB0

SELECTION

0

0

Color Index Mode

0

1

RGB Mode, 11101 + 8-bit address

1

0

RGB Mode, 11110 + 8-bit address

1

1

RGB Mode, 11111 + 8-bit address

These two bits are latched on the rising edge of CLOCK.IN.

PIPE.IN0–PIPE.IN3

These four input pins are provided for the video timing signals such as CBLANKB

and CSYNCB. Internally, these signals will go through the same number of

pipeline stages as the pixel data. The video timing signals will subseqently appear

at the PIPE.OUT outputs, and synchronized with the appropriate color data. These

inputs are also latched by the rising edge of CLOCK.IN.

CLOCK.IN

This is the clock input pin. The CLOCK.IN controls the latching output and

subsequent processing of the pixel data and video timing signals.

POUT0–POUT23

Color information output pins. POUT0–POUT7, POUT8–POUT15, and POUT16–

POUT23 are the red, green, and blue color data, respectively.

PIPE.OUT0–PIPE.OUT3

Video timing signals output pins. The output data is synchronized with the color

data is output on these pins. Fig. 1 describes internal pipeline data path flow.

CEB1, CEB2

The chip enable input pins. MPU read and write cycles are performed by bringing

either of these pins low. The falling edge of this signal latches information from the

R/WB, CONFIGSEL, and CONFIGBUS pins.

R/WB

Read and write control input pins. When latched by the falling edge of CEB, this

signal determines whether the following operation is a read or a write. A read

operation is performed when this signal is high, and a write operation is performed

when this signal is low.

CONFIGBUS0–CONFIGBUS7

These pins are used for data I/O. RAM and register data are input and output

through these pins. These pins are used for read and write to/from RAM and

register.

CONFIGSEL0–CONFIGSEL2

The device configuration input pins. These inputs specify the type of read or write

operation to perform. The particular RAM or register operation is defined by the

truth table. This information is latched on the falling edge of CEB.

CBLANKB

Blanking status input pin. This signal indicates to the device that a blanking period

is taking place so it is therefore permissible to change data in the palette RAM.

This pin is active low.