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ECP5 Versa Development Board

®

Table 8. Alpha-numeric LED Definitions

Display

FPGA Ball Number

Display

FPGA Ball Number

A

M20

J

N18

B

L18

K

P17

C

M19

L

N17

D

L16

M

P16

E

L17

N

R16

F

M18

P

R17

G

N16

DP

U1

H

M17

DDR3 Memory Device

(See Appendix A, Sheet 7, Figure 16 - DDR3 Memory)

• The ECP5 Versa Development Board is equipped with an SDRAM memory device (1.5 V, 64 Mb/x16, 96-ball

FBGA, 933 MHz, DDR3-1866) such as the Micron MT41K64M16TW-107:J device.

• The DDR3 memory includes a 16-bit wide memory controller interface.

• The board includes termination of data, address and command signals. It includes all power and external compo-

nents needed to demonstrate the memory controller of the ECP5 device.

• A 100 MHz on-board clock oscillator is available to provide a DDR3 reference clock.