ADC0808-N, ADC0809-N

SNAS535H – OCTOBER 1999 – REVISED MARCH 2013

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Electrical Characteristics – Timing Specifications (continued)

Timing Specifications VCC=VREF(+)=5V, VREF(−)=GND, tr=tf=20 ns and TA=25°C unless otherwise noted.

Symbol

Parameter

Conditions

MIn

Typ

Max

Units

tWS

Minimum Start Pulse Width

(Figure 7)

100

200

ns

tWALE

Minimum ALE Pulse Width

(Figure 7)

100

200

ns

ts

Minimum Address Set-Up Time

(Figure 7)

25

50

ns

tH

Minimum Address Hold Time

(Figure 7)

25

50

ns

tD

Analog MUX Delay Time From ALE

RS=0Ω (Figure 7)

1

2.5

μs

tH1, tH0

OE Control to Q Logic State

CL=50 pF, RL=10k (Figure 10)

125

250

ns

t1H, t0H

OE Control to Hi-Z

CL=10 pF, RL=10k (Figure 10)

125

250

ns

tc

Conversion Time

fc=640 kHz, (Figure 7)

(1)

90

100

116

μs

fc

Clock Frequency

10

640

1280

kHz

Clock

tEOC

EOC Delay Time

(Figure 7)

0

8 + 2

μS

Periods

CIN

Input Capacitance

At Control Inputs

10

15

pF

COUT

TRI-STATE Output Capacitance

At TRI-STATE Outputs

10

15

pF

(1)

The outputs of the data register are updated one clock cycle before the rising edge of EOC.

4

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