XIO2001IPNP datasheet(80/145 Pages) TI2

80 / 145 page

Table 8-49. General Control Register Description (continued)

BIT

FIELD NAME

ACCESS

DESCRIPTION

9:8(1)

MIN_POWER_SC

ALE

Minimum power scale. This value is programmed to indicate the scale of bits 7:0

(MIN_POWER_VALUE).

00 =

01 =

10 =

11 =

1.0x

0.1x

0.01x (default)

0.001x

7:0(1)

MIN_POWER_VA

LUE

Minimum power value. This value is programmed to indicate the minimum power requirements.

This value is multiplied by the minimum power scale field (bits 9:8) to determine the minimum

power requirements for the bridge. The default is 5Fh, indicating that the bridge requires 0.95 W

of power. This field can be reprogrammed through an EEPROM or the system BIOS.

(1)

These bits are reset by a PCI Express reset ( PERST), a GRST, or the internally-generated power-on reset.

(2)

These bits are sticky and must retain their value when the bridge is powered by VAUX.

8.4.67 Clock Control Register

This register enables and disables the PCI clock outputs (CLKOUT). See Table 8-50 for a complete description

of the register contents.

PCI register offset:

D8h

Read-only, Read/Write

Default value:

00h

BIT NUMBER

RESET STATE

Table 8-50. Clock Control Register Description

BIT

FIELD NAME

ACCESS

DESCRIPTION

7(1)

RSVD

Reserved. Returns 0b when read.

6(1)

CLOCK6_DISABLE

Clock output 6 disable. This bit disables secondary CLKOUT6.

0 = Clock enabled (default)

1 = Clock disabled

5(1)

CLOCK5_DISABLE

Clock output 5 disable. This bit disables secondary CLKOUT5.

0 = Clock enabled (default)

1 = Clock disabled

4(1)

CLOCK4_DISABLE

Clock output 4 disable. This bit disables secondary CLKOUT4.

0 = Clock enabled (default)

1 = Clock disabled

3(1)

CLOCK3_DISABLE

Clock output 3 disable. This bit disables secondary CLKOUT3.

0 = Clock enabled (default)

1 = Clock disabled

2(1)

CLOCK2_DISABLE

Clock output 2 disable. This bit disables secondary CLKOUT2.

0 = Clock enabled (default)

1 = Clock disabled

1(1)

CLOCK1_DISABLE

Clock output 1 disable. This bit disables secondary CLKOUT1.

0 = Clock enabled (default)

1 = Clock disabled

0(1)

CLOCK0_DISABLE

Clock output 0 disable. This bit disables secondary CLKOUT0.

0 = Clock enabled (default)

1 = Clock disabled

(1)

These bits are reset by a PCI Express reset ( PERST), a GRST, or the internally-generated power-on reset.

XIO2001

SCPS212J – MAY 2009 – REVISED JANUARY 2021

www.ti.com

Submit Document Feedback

Product Folder Links: XIO2001

XIO2001IPNP Datasheet(PDF) 80 Page - Texas Instruments

XIO2001IPNP Datasheet(HTML) 80 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Descarga

Enlace URL