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IS25LE01G-RILA3-TY Datasheet(PDF) 132 Page - Integrated Silicon Solution, Inc

No. de pieza IS25LE01G-RILA3-TY
Descripción Electrónicos  SERIAL FLASH MEMORY 133/104MHZ MULTI I/O SPI & QUAD I/O QPI DTR INTERFACE WITH ON-CHIP ECC
PDF  186 Pages
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Fabricante Electrónico  ISSI [Integrated Silicon Solution, Inc]
Página de inicio  http://www.issi.com
Logo ISSI - Integrated Silicon Solution, Inc

IS25LE01G-RILA3-TY Datasheet(HTML) 132 Page - Integrated Silicon Solution, Inc

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IS25LE01G
IS25WE01G
Integrated Silicon Solution, Inc.- www.issi.com
132
Rev. A6
01/14/2025
Figure 8.88 FRDDTR AX Read Sequence (BDh [EXTADD=0], 3-byte address)
IO0
IO1
3-byte Address
...
...
tV
22 20 18
7 5 3 1 7 5 3 1 7 5 3 1
4 Dummy Cycles
23 21 19
...
6 4 2 0 6 4 2 0 6 4 2 0
Data Out
Data Out
Data Out
16 14 12
17 15 13
10
11
SCK
0
1
2
...
6
7
8
9
10
11
12
13
14
15
16
Mode 3
Mode 0
CE #
7 5 3 1
6 4 2 0
0
1
Mode Bits
...
...
Notes:
1.
If the mode bits=AXh (where X is don’t care), it will keep executing the AX read mode (without command). When the
mode bits are different from AXh, the device exits the AX read operation.
2. Number of dummy cycles depends on clock speed. Detailed information in Table 6.11 Read Dummy Cycles.
3. Sufficient dummy cycles are required to avoid I/O contention. If the number of dummy cycles and AX bits cycles
are same, then X should be Hi-Z.
Figure 8.89 FRDDTR AX Read Sequence (BDh [EXTADD=1] or BEh, 4-byte address)
4-byte Address
...
30 28 26
31 29 27
24 22 20
25 23 21
18
19
8
9
10
11
12
13
14
15
16
17
18
IO0
IO1
...
tV
7 5 3 1 7 5 3 1 7 5 3 1
4 Dummy Cycles
...
6 4 2 0 6 4 2 0 6 4 2 0
Data Out
Data Out
Data Out
SCK
0
1
2
...
Mode 3
Mode 0
CE #
7 5 3 1
6 4 2 0
0
1
Mode Bits
...
...
Notes:
1.
If the mode bits=AXh (where X is don’t care), it will keep executing the AX read mode (without command). When the
mode bits are different from AXh, the device exits the AX read operation.
2. Number of dummy cycles depends on clock speed. Detailed information in Table 6.11 Read Dummy Cycles.
3. Sufficient dummy cycles are required to avoid I/O contention. If the number of dummy cycles and AX bits cycles
are same, then X should be Hi-Z.



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