ICS87421AMILF datasheet(7/14 Pages) IDT

No. de pieza	ICS87421AMILF

Descripción Electrónicos	첨1/첨2 DIFFERENTIAL-TO-LVDS CLOCK GENERATOR

PDF	14 Pages

Scroll/Zoom	100%

Fabricante Electrónico	IDT [Integrated Device Technology]

Página de inicio	http://www.idt.com

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IDT™ / ICS™ LVDS CLOCK GENERATOR

ICS87421AMI REV. A OCTOBER 3, 2007

ICS87421I

÷1/÷2 DIFFERENTIAL-TO-LVDS CLOCK GENERATOR

APPLICATION INFORMATION

Figure 2 shows how the differential input can be wired to accept

single ended levels. The reference voltage V_REF = V

/2 is

generated by the bias resistors R1, R2 and C1. This bias circuit

should be located as close as possible to the input pin. The ratio

FIGURE 2. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT

WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS

of R1 and R2 might need to be adjusted to position the V_REF in

the center of the input voltage swing. For example, if the input

clock swing is only 2.5V and V

= 3.3V, V_REF should be 1.25V

and R2/R1 = 0.609.

V_REF

0.1u

Single Ended Clock Input

CLK

nCLK

VDD

INPUTS:

LVCMOS CONTROL PINS

All control pins have internal pull-ups or pull-downs; additional

resistance is not required but can be added for additional

protection. A 1k

Ω resistor can be used.

RECOMMENDATIONS FOR UNUSED INPUT PINS

ICS87421AMILF Datasheet(PDF) 7 Page - Integrated Device Technology