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Motor de Búsqueda de Datasheet de Componentes Electrónicos |
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Motor de Búsqueda de Datasheet de Componentes Electrónicos |
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FC106 Datasheet(PDF) 15 Page - STMicroelectronics |
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FC106 Datasheet(HTML) 15 Page - STMicroelectronics |
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15 / 32 page  FC106 Revision 1.2 15/32 September 98 3.14 Self-test The self-test block generates its own internal clock (the frequency of which can be digitally tuned through the JTAG port), and pseudo-random patterns. This data is encoded, serialized, deserialized (through the loop-back test path, or through an external connection between TX+/TX- and RX+/RX-) and decoded. The recovered data is checked; the errors and the number of transmitted bytes are internally counted. The contents of these counters are accessible through the JTAG path. This block is activated by the AT signal. In normal operation, AT is tied to Vdd and the self-test block is disabled. During production tests, AT is forced to Vss, allowing full speed dynamic tests, even at wafer level. |
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