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ICS841S02BGILF Datasheet(PDF) 3 Page - Integrated Device Technology

No. de pieza ICS841S02BGILF
Descripción Electrónicos  PCI EXPRESS??CLOCK GENERATOR
PDF  17 Pages
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Fabricante Electrónico  IDT [Integrated Device Technology]
Página de inicio  http://www.idt.com
Logo IDT - Integrated Device Technology

ICS841S02BGILF Datasheet(HTML) 3 Page - Integrated Device Technology

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IDT™ / ICS™ PCI EXPRESS CLOCK GENERATOR
3
ICS841S02BGI REV. C NOVEMBER 1, 2007
ICS841S02I
PCI EXPRESS™ CLOCK GENERATOR
PRELIMINARY
To enhance the flexibility and function of the clock synthesizer,
a two-signal serial interface is provided. Through the Serial Data
Interface, various device functions, such as individual clock
output buffers, can be individually enabled or disabled. The
registers associated with the Serial Data Interface initialize to
their default setting upon power-up, and therefore, use of this
interface is optional. Clock device register changes are nor-
mally made upon system initialization, if any are required. The
interface cannot be used during system operation for power
management functions.
SERIAL DATA INTERFACE
The clock driver serial protocol accepts byte write, byte read,
block write, and block read operations from the controller. For
block write/read operation, the bytes must be accessed in se-
quential order from lowest to highest byte (most significant bit
first) with the ability to stop after any complete byte has been
transferred. For byte write and byte read operations, the sys-
tem controller can access individually indexed bytes. The off-
set of the indexed byte is encoded in the command code, as
described in Table 3A.
The block write and block read protocol is outlined in Table 3B,
while Table 3C outlines the corresponding byte write and byte
read protocol. The slave receiver address is 11010010 (D2h).
DATA PROTOCOL
TABLE 3A. COMMAND CODE DEFINITION
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