Architecture

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Figure 9: High-level detection architecture

In the architecture illustrated in Figure 9: "High-level detection architecture" we have:

•

8 RMS meters detailed in Section 5.3.5: "Averaging based RMS calculation"

−

The RMS calculation can be enabled using the dedicated I²C register (Reg. 0x11

and Reg. 0x12).

•

8 digital comparators to detect a high level on the related channel. The threshold value

for each channel can be programmed through the dedicated I²C register RMS_TH

(Reg. 0x0F and 0x10). Moreover observing Figure 9: "High-level detection

architecture" it is possible to see that two threshold programming modalities are

supported:

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Single threshold programming: using the COMP_SEL I²C register (Reg. 0x0E,

bit B6, B5 and B4) it is possible to select and consequently to program the

desired comparator threshold. In this case one single threshold can be

programmed every time.

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Burst threshold programming: using the COMP_B I²C register (Reg. 0x0E, bit

B7) it is possible to program the same threshold at the input of each comparator.

When a channel level exceeds the high-level limit programmed through the I²C, the

corresponding bit in the I²C register RMSxS (Reg. 0x24) is set to one and an interrupt is

generated.

Furthermore the RMS value of each channel can be read back, reading the related I²C

registers RMS_CHx (from Reg. 0x13 to Reg. 0x22), and its value in dB is given by the

following equation:

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