LP8557IAYFQR datasheet(39/49 Pages) TI2

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ILED1

GNDs

LP8557

Up to 28V

Parasitic

PCB

Inductances

Current through

inductor

Pulsed voltage at SW

Voltage Spike

LCD Display

ISET/SCL

FSET/SDA

VDD

COUT

Current through

Schottky Diode and COUT

2.7V to 5.5V

Affected Node

due to capacitive

coupling

Cp1

Lp1

Lp2

Lp3

IAVE = IIN

IPEAK

VOUT + VF Schottky

ILED6

PWM/INT

LP8557, LP85571

www.ti.com

SNVSA15B – DECEMBER 2013 – REVISED DECEMBER 2015

Figure 48. LP8557 Inductive Boost Converter Showing Pulsed Voltage at SW (High dv/dt) And Current

Through the Schottky Diode and COUT (High di/dt)

The following list details the main (layout sensitive) areas of the LP8557’s inductive boost converter in order of

decreasing importance:

1. Output Capacitor

–

COUT+ to Schottky diode cathode connection

–

COUT– to GND bump of the LP8557 connection

2. Schottky Diode

–

Schottky diode anode to SW connection

–

Schottky diode cathode to COUT+ connection

3. Inductor

–

SW Node PCB capacitance to other traces

4. Input Capacitor

–

CIN+ to VDD bump connection

–

CIN– to GND connection

11.1.1 Boost Output Capacitor Placement

Because the output capacitor is in the path of the inductor current discharge path, it detects a high-current step

from 0 to IPEAK each time the switch turns off and the Schottky diode turns on. Any inductance along this series

path from the diodes cathode, through COUT, and back into the LP8557 GND pin contributes to voltage spikes

(VSPIKE = LP_ × dI/dt) at SW and OUT. These spikes can potentially over-voltage the SW and FB pins, or feed

through to GND. To avoid this, COUT+ must be connected as close to the cathode of the Schottky diode as

possible, and COUT

− must be connected as close to the LP8557 GND pins as possible. The best placement for

COUT is on the same layer as the LP8557 to avoid any vias that can add excessive series inductance.

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LP8557IAYFQR Datasheet(PDF) 39 Page - Texas Instruments

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