7 Detailed Description

7.1 Overview

The CDx4HC640 and CDx4HCT640 silicon-gate CMOS three-state bidirectional inverting and non-inverting

buffers are intended for two-way asynchronous communication between data buses. They have high drive

current outputs which enable high-speed operation when driving large bus capacitances. These circuits possess

the low power dissipation of CMOS circuits, and have speeds comparable to low power Schottky TTL circuits.

They can drive 15 LSTTL loads. The CDx4HC640 and CDx4HCT640 devices have inverting buffers.

The direction of data flow (A to B, B to A) is controlled by the DIR input.

Outputs are enabled by a low on the Output Enable input (OE); a high OE puts these devices in the high

impedance mode.

7.2 Functional Block Diagram

7.3 Device Functional Modes

Table 7-1. Function Table

(2)

Control Inputs(1)

Data Port Status

OE

DIR

An

Bn

L

L

O

I

H

H

Z

Z

H

L

Z

Z

L

H

I

O

(1)

H = High level. L = Low level. I = Input. O = Output (inversion of

input level). Z = High impedance.

(2)

To prevent excess currents in the High-Z modes all I/O terminals

should be terminated with 1kΩ to 1MΩ resistors.

CD54HC640, CD74HC640, CD54HCT640, CD74HCT640

SCHS192C – NOVEMBER 1998 – REVISED JULY 2022

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