PL133-47

Low-Power 2.25V to 3.63V DC to 150MHz 1:4 Fanout Buffer IC

Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1(408) 944 -0800 • fax +1(408) 474-1000 • www.micrel.com Rev 1/27/11 Page 2

PIN DESCRIPTIONS

Name

SOP-8L

Type

Description

REF

3

I

Input reference frequency.

CLK0

5

O

Buffered clock output

CLK1

6

O

Buffered clock output

CLK2

7

O

Buffered clock output

CLK3

8

O

Buffered clock output

VDD

1, 2

P

VDD connection

GND

4

P

GND connection

LAYOUT RECOMMENDATIONS

The following guidelines are to assist you with a performance optimized PCB d esign:

Signal Integrity and Termination

Considerations

- Keep traces short!

- Trace = Inductor. With a capacitive load this equals

ringing!

- Long trace = Transmission Line. Without proper termi-

nation this will cause reflections ( looks like ringing ).

- Design long traces (> 1 inch) as “striplines” or

“microstrips” with defined impedance.

- Match trace at one side to avoid refl ections bouncing

back and forth.

Decoupling and Power Supply

Considerations

- Place decoupling capacitors as close as possible

to the VDD pin(s) to limit noise from the power

supply

- Addition of a ferrite bead in series with VDD can

help prevent noise from other board sources

- Value of decoupling capacitor is frequency de-

pendant. Typical values to use are 0.1

F for de-

signs using frequencies < 50MHz and 0.01

F for

designs using frequencies > 50MHz.

Typical CMOS termination

Place Series Resistor as close as possible to CMOS output

CMOS Output Buffer

( Typical buffer impedance 20 ohm)

To CMOS Input

Connect a 33 ohm series resistor at each of the output clocks to

enhance the stability of the output signal

50 ohm line