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TMS320VC33 Datasheet(PDF) 49 Page - Texas Instruments

No. de pieza TMS320VC33
Descripción Electrónicos  DIGITAL SIGNAL PROCESSOR
PDF  59 Pages
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Fabricante Electrónico  TI2 [Texas Instruments]
Página de inicio  https://www.ti.com
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TMS320VC33 Datasheet(HTML) 49 Page - Texas Instruments

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TMS320VC33
DIGITAL SIGNAL PROCESSOR
SPRS087E -- FEBRUARY 1999 -- REVISED JANUARY 2004
49
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251--1443
general-purpose I/O timing
Peripheral pins include CLKX0, CLKR0, DX0, DR0, FSX0, FSR0, and TCLK0/1. The contents of the internal
control registers associated with each peripheral define the modes for these pins.
peripheral pin I/O timing
The following tables show the timing parameters for changing the peripheral pin from a general-purpose output
pin to a general-purpose input pin and vice versa.
timing requirements for peripheral pin general-purpose I/O (see Note 1, Figure 35, and Figure 36)
VC33-120
VC33-150
UNIT
MIN
MAX
MIN
MAX
UNIT
tsu(GPIO-H1L)
Setup time, general-purpose input before H1 low
4
3
ns
th(H1L-GPIO)
Hold time, general-purpose input after H1 low
0
0
ns
NOTE 1: Peripheral pins include CLKX0, CLKR0, DX0, DR0, FSX0, FSR0, and TCLK0/1. The modes of these pins are defined by the contents
of internal-control registers associated with each peripheral.
switching characteristics over recommended operating conditions for peripheral pin
general-purpose I/O (see Note 1, Figure 35, and Figure 36)
PARAMETER
VC33-120
VC33-150
UNIT
PARAMETER
MIN
MAX
MIN
MAX
UNIT
td(H1H-GPIO)
Delay time, H1 high to general-purpose output
5
4
ns
tdis(H1H)
Disable time, general-purpose output from H1 high
7
5
ns
NOTE 1: Peripheral pins include CLKX0, CLKR0, DX0, DR0, FSX0, FSR0, and TCLK0/1. The modes of these pins are defined by the contents
of internal-control registers associated with each peripheral.
Value on Pin
Seen in
Peripheral-
Control Register
Synchronizer Delay
Buffers Go
From Output to
Input
Execution of
Store of
Peripheral-Cont
rol Register
Data Bit
I/O
Control Bit
H1
H3
Output
Data
Seen
Data Sampled
Peripheral Pin
(see Note A)
tsu(GPIO-H1L)
th(H1L-GPIO)
tdis(H1H)
NOTE A: Peripheral pins include CLKX0, CLKR0, DX0, DR0, FSX0, FSR0, and TCLK0/1.
Figure 35. Change of Peripheral Pin From General-Purpose Output to Input Mode Timing



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