7 Detailed Description

7.1 Overview

Information at the data (D) inputs meeting the setup time requirements is transferred to the outputs on the

positive-going edge of the clock (CLK) pulse. Clock triggering occurs at a particular voltage level and is not

directly related to the transition time of the positive-going edge of CLK. When CLK is at either the high or low

level, the D input has no effect at the output.

7.2 Functional Block Diagram

Figure 7-1. Logic Diagram (Positive Logic)

7.3 Device Functional Modes

Table 7-1. Function Table (Each Flip-flop)

INPUTS

OUTPUT

CLR

CLK

D

Q

Q

L

X

X

L

H

H

↑

H

H

L

H

↑

L

L

H

H

L

X

Q0

Q 0

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CD74ACT175

SCHS345A – APRIL 2003 – REVISED MAY 2024

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