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TS5MP645YFPR Datasheet(PDF) 8 Page - Texas Instruments |
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TS5MP645YFPR Datasheet(HTML) 8 Page - Texas Instruments |
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8 / 33 page  8 TS5MP645 SCDS385B – JANUARY 2018 – REVISED JULY 2018 www.ti.com Product Folder Links: TS5MP645 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated Electrical Characteristics (continued) Over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT DIGITAL CHARACTERISTICS VIH Input logic high (SEL, OE) VI/O = 0.6 V, RL = 50 Ω, CL = 5 pF 1.425 5.5 V VIL Input logic low (SEL, OE) VI/O = 0.6 V, RL = 50 Ω, CL = 5 pF 0 0.5 V IIH Input high leakage current (SEL, OE) VI/O = 0.6 V, RL = 50 Ω, CL = 5 pF -5 5 µA IIL Input low leakage current (SEL, OE) VI/O = 0.6 V, RL = 50 Ω,CL = 5 pF -5 5 µA RPD Internal pull-down resistance on digital input pins VI/O = 0.6 V, RL = 50 Ω, CL = 5 pF 6 MΩ CSEL, COE Digital Input capacitance (SEL, OE) f = 1 MHz 5 pF |
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