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DS20006788A-page 13

ZL40264

FIGURE 2-8:

Power Supply Filtering.

2.6

Power Supplies and Power-up Sequence

The device has two different power supplies: VDD and VDDO which should always be connected to the same voltage

supply. Voltages supported by each of these power supplies are specified in Table 3-2.

VDD and VDDO should always be turned on and off at the same time.

2.7

Device Control

ZL40264 outputs are controlled via OE[3:0]_b pins. When an OE_b pin is low the corresponding outputs will be active

and when this pin is high the output will be high-Z. When the output driver is in high-Z mode, the output pins will be

pulled low via external 50Ω HCSL termination resistors.

2.8

Typical phase noise performance

The following plots show typical phase noise performance for 100 MHz, 133 MHz, 400 MHz, and 491.52 MHz clocks

respectively.

FIGURE 2-9:

100 MHz HCSL Phase Noise.