ADC12D040CIVSSLASHNOPB datasheet(5/31 Pages) TI2

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ADC12D040

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SNAS171E – JUNE 2002 – REVISED MARCH 2013

PIN DESCRIPTIONS AND EQUIVALENT CIRCUITS (continued)

Pin No.

Symbol

Equivalent Circuit

Description

24–29

DA0–DA11

34–39

Digital data output pins that make up the 12-bit conversion results of

their respective converters. DA0 and DB0 are the LSBs, while DA11

and DB11 are the MSBs of the output word. Output levels are

42–47

DB0–DB11

TTL/CMOS compatible.

52–57

ANALOG POWER

Positive analog supply pins. These pins should be connected to a

9, 18, 19,

quiet +5V source and bypassed to AGND with 0.1 µF monolithic

62, 63

capacitors located within 1 cm of these power pins, and with a 10 µF

capacitor.

3, 8, 10, 17,

AGND

The ground return for the analog supply.

20, 61, 64

DIGITAL POWER

Positive digital supply pin. This pin should be connected to the same

quiet +5V source as is VA and be bypassed to DGND with a 0.1 µF

33, 48

monolithic capacitor located within 1 cm of the power pin and with a

10 µF capacitor.

32, 49

DGND

The ground return for the digital supply.

Positive digital supply pins for the ADC12D040's output drivers.

These pins should be connected to a voltage source of +2.4V to +5V

and bypassed to DR GND with a 0.1 µF monolithic capacitor. If the

30, 51

VDR

supply for these pins are different from the supply used for VA and

VD, they should also be bypassed with a 10 µF tantalum capacitor.

VDR should never exceed the voltage on VD. All bypass capacitors

should be located within 1 cm of the supply pin.

The ground return for the digital supply for the ADC12D040's output

drivers. These pins should be connected to the system digital

23, 31, 40,

DR GND

ground, but not be connected in close proximity to the ADC12D040's

50, 58

DGND or AGND pins. See LAYOUT AND GROUNDING (Layout and

Grounding) for more details.

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