PIC16F753 datasheet(56/230 Pages) MICROCHIP

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PIC16F753/HV753

DS40001709C-page 56

 2013-2015 Microchip Technology Inc.

6.2

OPTION_REG: OPTION REGISTER

R/W-1

RAPU

INTEDG

T0CS

T0SE

PSA

PS<2:0>

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n = Value at POR

‘1’ = Bit is set

‘0’ = Bit is cleared

x = Bit is unknown

bit 7

RAPU: PORTA Pull-up Enable bit

= PORTA pull-ups are disabled

= PORTA pull-ups are enabled by individual PORT latch values in WPU register

bit 6

INTEDG: Interrupt Edge Select bit

= Interrupt on rising edge of INT pin

= Interrupt on falling edge of INT pin

bit 5

T0CS: TMR0 Clock Source Select bit

= Transition on T0CKI pin

= Internal instruction cycle clock (FOSC/4)

bit 4

T0SE: TMR0 Source Edge Select bit

= Increment on high-to-low transition on T0CKI pin

= Increment on low-to-high transition on T0CKI pin

bit 3

PSA: Prescaler Assignment bit

= Prescaler is assigned to the WDT

= Prescaler is assigned to the Timer0 module

bit 2-0

PS<2:0>: Prescaler Rate Select bits

000

001

010

011

100

101

110

111

1 : 2

1 : 4

1 : 8

1 : 16

1 : 32

1 : 64

1 : 128

1 : 256

1 : 1

1 : 2

1 : 4

1 : 8

1 : 16

1 : 32

1 : 64

1 : 128

Bit Value

TMR0 Rate

WDT Rate

TABLE 6-1:

SUMMARY OF REGISTERS ASSOCIATED WITH TIMER0

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Page

TMR0

TMR0<7:0>

54*

INTCON

GIE

PEIE

T0IE

INTE

IOCIE

T0IF

INTF

IOCIF

OPTION_REG

RAPU

INTEDG

T0CS

T0SE

PSA

PS<2:0>

TRISA

—

TRISA5

TRISA4

TRISA3(1)

TRISA2

TRISA1

TRISA0

Legend:

– = Unimplemented locations, read as ‘0’, u = unchanged, x = unknown. Shaded cells are not used by the Timer0

module.

Page provides register information.

Note

TRISA3 always reads ‘1’.

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