PIC12LF1501 datasheet(170/352 Pages) MICROCHIP

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PIC16(L)F1503

DS40001607D-page 170

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21.4.9

ACKNOWLEDGE SEQUENCE

The ninth SCLx pulse for any transferred byte in I2C is

dedicated as an Acknowledge. It allows receiving

devices to respond back to the transmitter by pulling

the SDAx line low. The transmitter must release con-

trol of the line during this time to shift in the response.

The Acknowledge (ACK) is an active-low signal, pull-

ing the SDAx line low indicated to the transmitter that

the device has received the transmitted data and is

ready to receive more.

The result of an ACK is placed in the ACKSTAT bit of

the SSPxCON2 register.

Slave software, when the AHEN and DHEN bits are

set, allow the user to set the ACK value sent back to

the transmitter. The ACKDT bit of the SSPxCON2 reg-

ister is set/cleared to determine the response.

Slave hardware will generate an ACK response if the

AHEN and DHEN bits of the SSPxCON3 register are

clear.

There are certain conditions where an ACK will not be

sent by the slave. If the BF bit of the SSPxSTAT regis-

ter or the SSPOV bit of the SSPxCON1 register are

set when a byte is received.

When the module is addressed, after the eighth falling

edge of SCLx on the bus, the ACKTIM bit of the

SSPxCON3 register is set. The ACKTIM bit indicates

the acknowledge time of the active bus. The ACKTIM

Status bit is only active when the AHEN bit or DHEN

bit is enabled.

21.5

I2C

Slave Mode Operation

The MSSP Slave mode operates in one of four modes

selected in the SSPM bits of SSPxCON1 register. The

modes can be divided into 7-bit and 10-bit Addressing

mode. 10-bit Addressing modes operate the same as

7-bit with some additional overhead for handling the

larger addresses.

Modes with Start and Stop bit interrupts operate the

same as the other modes with SSPxIF additionally

getting set upon detection of a Start, Restart, or Stop

condition.

21.5.1

SLAVE MODE ADDRESSES

The SSPxADD register (Register 21-6) contains the

Slave mode address. The first byte received after a

Start or Restart condition is compared against the

value stored in this register. If the byte matches, the

value is loaded into the SSPxBUF register and an

interrupt is generated. If the value does not match, the

module goes idle and no indication is given to the soft-

ware that anything happened.

The SSP Mask register (Register 21-5) affects the

address matching process. See Section21.5.9 “SSPx

Mask Register”

for more information.

21.5.1.1

I2C Slave 7-bit Addressing Mode

In 7-bit Addressing mode, the LSb of the received data

byte is ignored when determining if there is an address

match.

21.5.1.2

I2C Slave 10-bit Addressing Mode

In 10-bit Addressing mode, the first received byte is

compared to the binary value of ‘1 1 1 1 0 A9 A8 0’. A9

and A8 are the two MSbs of the 10-bit address and

stored in bits 2 and 1 of the SSPxADD register.

After the acknowledge of the high byte the UA bit is set

and SCLx is held low until the user updates SSPxADD

with the low address. The low address byte is clocked

in and all eight bits are compared to the low address

value in SSPxADD. Even if there is not an address

match; SSPxIF and UA are set, and SCLx is held low

until SSPxADD is updated to receive a high byte

again. When SSPxADD is updated the UA bit is

cleared. This ensures the module is ready to receive

the high address byte on the next communication.

A high and low address match as a write request is

required at the start of all 10-bit addressing communi-

cation. A transmission can be initiated by issuing a

Restart once the slave is addressed, and clocking in

the high address with the R/W bit set. The slave hard-

ware will then acknowledge the read request and pre-

pare to clock out data. This is only valid for a slave

after it has received a complete high and low address

byte match.

21.5.2

SLAVE RECEPTION

When the R/W bit of a matching received address byte

is clear, the R/W bit of the SSPxSTAT register is

cleared. The received address is loaded into the

SSPxBUF register and acknowledged.

When the overflow condition exists for a received

address, then not Acknowledge is given. An overflow

condition is defined as either bit BF of the SSPxSTAT

is set. The BOEN bit of the SSPxCON3 register modi-

fies this operation. For more information see

An MSSP interrupt is generated for each transferred

data byte. Flag bit, SSPxIF, must be cleared by soft-

ware.

When the SEN bit of the SSPxCON2 register is set,

SCLx will be held low (clock stretch) following each

received byte. The clock must be released by setting

the CKP bit of the SSPxCON1 register, except

sometimes in 10-bit mode. See Section21.2.3 “SPI

Master Mode”

for more detail.

21.5.2.1

7-bit Addressing Reception

This section describes a standard sequence of events

for the MSSP module configured as an I2C slave in

7-bit Addressing mode. Figure 21-14 and Figure 21-15

are used as visual references for this description.

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