R1

4.1V

R3

R2

0.1 PF

U3

LM4040

R4

VOUT

V+

VT

VTemp

+

-

U1

LM19

V+

U2

(High = overtemp alarm)

VT1

VT2

VTEMP

VOUT

VT1 =

R1 + R2||R3

(4.1)R2

VT2 =

R2 + R1||R3

(4.1)R2||R3

LM7211

LM19

SNIS122E – MAY 2001 – REVISED MARCH 2013

www.ti.com

Applications Circuits

Figure 5. Centigrade Thermostat

Figure 6. Conserving Power Dissipation with Shutdown

Figure 7. Suggested Connection to a Sampling Analog to Digital Converter Input Stage

Most CMOS ADCs found in ASICs have a sampled data comparator input structure that is notorious for causing

grief to analog output devices such as the LM19 and many op amps. The cause of this grief is the requirement of

instantaneous charge of the input sampling capacitor in the ADC. This requirement is easily accommodated by

the addition of a capacitor. Since not all ADCs have identical input stages, the charge requirements will vary

necessitating a different value of compensating capacitor. This ADC is shown as an example only. If a digital

output temperature is required please refer to devices such as the LM74.

8

Submit Documentation Feedback

Copyright © 2001–2013, Texas Instruments Incorporated

Product Folder Links: LM19