PCA2129TSLASHQ900SLASH2 datasheet(52/84 Pages) NXP

52 / 84 page

PCA2129

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Product data sheet

Rev. 5 — 19 December 2014

52 of 84

NXP Semiconductors

PCA2129

Automotive accurate RTC with integrated quartz crystal

[1]

The chip enable must not be wired permanently LOW.

9.1.1 Data transmission

The chip enable signal is used to identify the transmitted data. Each data transfer is a

whole byte, with the Most Significant Bit (MSB) sent first.

The transmission is controlled by the active LOW chip enable signal SDA/CE. The first

byte transmitted is the command byte. Subsequent bytes are either data to be written or

data to be read (see Figure 29).

The command byte defines the address of the first register to be accessed and the

read/write mode. The address counter will auto increment after every access and will

reset to zero after the last valid register is accessed. The R/W bit defines if the following

bytes are read or write information.

Table 75.

Serial interface

Symbol

Function

Description

SDA/CE

chip enable input;

active LOW

[1] when HIGH, the interface is reset;

input may be higher than VDD

SCL

serial clock input

when SDA/CE is HIGH, input may float;

input may be higher than VDD

SDI

serial data input

when SDA/CE is HIGH, input may float;

input may be higher than VDD;

input data is sampled on the rising edge of

SCL

SDO

serial data output

push-pull output;

drives from VSS to Voper(int) (VBBS);

output data is changed on the falling edge of

SCL

Fig 29. Data transfer overview

Table 76.

Command byte definition

Bit

Symbol

Value

Description

7R/W

data read or write selection

write data

read data

6 to 5

subaddress;

other codes will cause the device to ignore

data transfer

4 to 0

00h to 1Bh

PCA2129T/Q900/2 Datasheet(PDF) 52 Page - NXP Semiconductors

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