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AX88796BLF Datasheet(PDF) 41 Page - ASIX Electronics Corporation |
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AX88796BLF Datasheet(HTML) 41 Page - ASIX Electronics Corporation |
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41 / 82 page ![]() ASIX ELECTRONICS CORPORATION 41 AX88796BLF / AX88796BLI 5.1.24 Interrupt mask register (IMR) Page0 Offset 0FH (Write) Field Name Description 7 Reserved 6 RDCE DMA Complete Interrupt Enable. Default “low” disabled. 5 CNTE Counter Overflow Interrupt Enable. Default “low” disabled. 4 OVWE Overwrite Interrupt Enable. Default “low” disabled. 3 TXEE Transmit Error Interrupt Enable. Default “low” disabled. 2 RXEE Receive Error Interrupt Enable. Default “low” disabled. 1 PTXE Packet Transmitted Interrupt Enable. Default “low” disabled. 0 PRXE Packet Received Interrupt Enable. Default “low” disabled. 5.1.25 Frames Lost Tally Register (CNTR2) Page0 Offset 0FH (Read) Field Name Description (Default = 00h) 7:0 CNTR2 This counter is incremented if a packet cannot be received due to lack of buffer resources. In monitor mode, this counter will count the number of packets that pass the address recognition logic. |
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