SN75176A

DIFFERENTIAL BUS TRANSCEIVER

SLLS100A – JUNE 1984 – REVISED MAY 1995

8

POST OFFICE BOX 655303

VOLTAGE WAVEFORMS

5 V

VOL

0.5 V

tPZL

3 V

0 V

tPLZ

2.3 V

1.5 V

Output

Input

TEST CIRCUIT

Output

RL = 110 Ω

5 V

S1

CL = 50 pF

(see Note B)

50

Ω

3 V or 0

Generator

(see Note A)

1.5 V

NOTES: A. The input pulse is supplied by a generator having the following characteristics: PRR = 1 MHz, 50% duty cycle, tr ≤ 6 ns, tf ≤ 6 ns,

ZO = 50 Ω.

B. CL includes probe and jig capacitance.

Figure 5. Driver Test Circuit and Voltage Waveforms

VOLTAGE WAVEFORMS

1.3 V

0 V

3 V

VOL

VOH

tPHL

tPLH

1.5 V

Output

Input

TEST CIRCUIT

CL = 15 pF

(see Note B)

Output

0 V

1.5 V

51

Ω

Generator

(see Note A)

1.5 V

1.3 V

NOTES: A. The input pulse is supplied by a generator having the following characteristics: PRR = 1 MHz, 50% duty cycle, tr ≤ 6 ns, tf ≤ 6 ns,

ZO = 50 Ω.

B. CL includes probe and jig capacitance.

Figure 6. Receiver Test Circuit and Voltage Waveforms