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Integer to Floating Point Pipelined Converter

ver 2.32

OVERVIEW

The DINT2FP is the pipelined integer to

floating point converter. The input and output

numbers format is according to IEEE-754

standard. DINT2FP supports double word

integers (4 Bytes) and single precision real

numbers. Convert operation is pipelined to 3

levels. Input data are fed every clock cycle.

The first result appears after latency equal to

3 clock periods and next results are available

each clock

cycle. Full precision and accu-

racy are accomplished.

APPLI C ATION

Math coprocessors

DSP algorithms

Embedded arithmetic coprocessor

Data processing & control

KEY FEATURES

Full IEEE-754 compliance

Double word integer input numbers (4

Bytes)

Single precision real output numbers

Simple interface

No programming required

3 levels pipelining

Full accuracy and precision

Results available at every clock

Fully configurable

Fully synthesizable, static synchronous

design with no internal tri-states

DELIVERABLES

Source code:

VHDL Source Code or/and

VERILOG Source Code or/and

VHDL & VERILOG test bench environ-

ment

Active-HDL automatic simulation mac-

ros

ModelSim automatic simulation macros

NCSim automatic simulation macros

Tests with reference responses

Technical documentation

Installation notes

HDL core specification

Datasheet

Synthesis scripts

Example application

Technical support

IP Core implementation support

3 months maintenance

●

Delivery the IP Core updates, minor

and major versions changes

●

Delivery the documentation updates

●

Phone & email support

LICENSING

Comprehensible and clearly defined licensing

methods without royalty fees make using of

IP Core easy and simply.

Single Design

license allows using IP Core in

single FPGA bitstream and ASIC implemen-