TMP93CS41 datasheet(189/248 Pages) TOSHIBA

189 / 248 page

TMP93CS40/TMP93CS41

2004-02-10

93CS40-187

12. Signal generating timing

1) In UART mode

Receive

Mode

9 Bits

8 Bits

+ Parity

8 Bits, 7 Bits

+ Parity, 7 Bits

Timing for interrupt

generation

Around center of bit8

Around center of

parity bit

Around center of stop bit

Timing for framing

generation

Around center of

stop bit

Around center of

stop bit

Around center of stop bit

Timing for parity

error generation

−

Around center of

parity bit

←

Timing for overrun

error timing

Around center of bit8

Around center of

parity bit

Around center of stop bit

Note: In 9-Bit and 8-Bit

+ Parity mode, interrupts coincide with the ninth bit pulse.Thus,

when servicing the interrupt, it is necessary to wait for a 1-bit period (to allow the stop

bit to be transferred) to allow checking for a framing error.

Send

Mode

9 Bits

8 Bits + Parity

8 Bits, 7 Bits + Parity, 7 Bits

Timing for interrupt

generation

Immediately before

stop bit sent

←

2) In I/O interface mode

SCLK0 output mode

Immediately after rise of last SCLK0 signal (See Figure 3.9.20)

Timing for send

interrupt

generation

SCLK0 input mode

Immediately after rise (Rising mode) or fall (Falling mode) of

last SCLK0 signal (See Figure 3.9.21)

SCLK0 output mode

Immediately after final SCLK0 (when received data are

transferred to receive buffer 2 (SC0BUF)) (See Figure 3.9.22)

Timing for

receive interrupt

generation

SCLK0 input mode

Immediately after final SCLK0 (when received data are

transferred to receive buffer 2 (SC0BUF)) (See Figure 3.9.23)

TMP93CS41 Datasheet(PDF) 189 Page - Toshiba Semiconductor

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