74ALVC573D datasheet(8/17 Pages) NXP

8 / 17 page

74ALVC573_3

Product data sheet

Rev. 03 — 26 October 2007

8 of 17

NXP Semiconductors

74ALVC573

Octal D-type transparent latch; 3-state

[1]

Typical values are measured at Tamb =25 °C

[2]

tpd is the same as tPHL and tPLH.

ten is the same as tPZH and tPZL.

tdis is the same as tPHZ and tPLZ.

[3]

CPD is used to determine the dynamic power dissipation (PD in µW).

PD =CPD × VCC2 × fi × N+ Σ(CL × VCC2 × fo) where:

fi = input frequency in MHz; fo = output frequency in MHz

CL = output load capacitance in pF

VCC = supply voltage in Volts

N = number of inputs switching

Σ(C

L × VCC

× f

o) = sum of the outputs

pulse width

LE pulse width HIGH; see Figure 9

VCC = 1.65 V to 1.95 V

3.8

VCC = 2.3 V to 2.7 V

3.3

VCC = 2.7 V

3.3

VCC = 3.0 V to 3.6 V

3.3

tsu

set-up time

Dn to LE; see Figure 11

VCC = 1.65 V to 1.95 V

0.8

VCC = 2.3 V to 2.7 V

0.8

VCC = 2.7 V

0.8

VCC = 3.0 V to 3.6 V

0.8

hold time

Dn to LE; see Figure 11

VCC = 1.65 V to 1.95 V

0.8

VCC = 2.3 V to 2.7 V

0.8

VCC = 2.7 V

0.8

VCC = 3.0 V to 3.6 V

0.7

CPD

power dissipation

capacitance

per latch; VI = GND to VCC; VCC = 3.3 V

[3]

outputs HIGH or LOW state

outputs 3-state

Table 7.

Dynamic characteristics …continued

Voltages are referenced to GND (ground = 0 V). For test circuit see Figure 12.

Symbol

Parameter

Conditions

−40 °C to +85 °C

Unit

Min

Typ[1]

Max

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