FXLS8971CF datasheet(22/100 Pages) NXP

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NXP Semiconductors

FXLS8971CF

3-Axis Low-g Accelerometer

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tHCS

tSCLKL

tSCLKH

tSCLK

tSCS

tSET

tHOLD

tWCS

SPI_CS_B

SCLK

SPI_MOSI

SPI_MISO

tDDLY

tHZ

High-Impedance

Figure 15. SPI timing diagram (4-wire mode)

13.6 SPI timing specifications (software enabled 3-wire mode)

Table 14 and Figure 16 specify and illustrate the minimum and maximum timing parameter values for correct

SPI interface functionality when FXLS8971CF is operated in 3-wire (software enabled) SPI mode. FXLS8971CF

only supports SPI mode '00', corresponding to CPOL = 0, and CPHA = 0. In this mode, the active state of the

clock is high and the idle state is low. Data is latched on the rising edge of the clock and propagated on the

falling edge. All timing specifications shown in Table 14 were determined under the following conditions: 10 pF

capacitor and 1 kΩ pull-up resistor present on all SPI signals, 105 °C, 1.8 V.

Note: When FXLS8971CF is operated in 3-wire SPI mode - by setting SENS_CONFIG1[SPI_M] = 1 - the

SA0/SPI_MISO pin is always placed in a high impedance (high-z) state, with the SPI_MISO pin output driver

disabled (tri-stated).

Specifications

Label

Description

Min.

Max.

Unit

fSCLK

SCLK frequency

MHz

tSCLK

SCLK Period

250

—

tSCLKH

SCLK high time

100

—

tSCLKL

SCLK low time

100

—

tSCS

Setup time for SPI_CS_B signal

125

—

tHCS

Hold time for SPI_CS_B signal

240

—

tHZ

Hold time for SPI_DATA signal transition

back to high-impedance state

—

tWCS

Inactive time for SPI_CS_B signal

600

—

tSET

Data setup time for SPI_DATA signal

—

tHOLD

Data hold time for SPI_DATA signal

—

tDDLY

Data setup time for SPI_DATA signal (output

phase)

—

Table 14. Secondary timing values

FXLS8971CF

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 2.1 — 7 March 2024

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