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High Speed CMOS Logic – 54HC00

Rev 1.0

07/02/19

COORDINATES (mm)

PAD

FUNCTION

X

Y

1

1A

0.132

0.443

2

1B

0.132

0.126

3

1Y

0.315

0.129

4

2A

0.485

0.128

5

2B

0.802

0. 129

6

2Y

0.981

0.129

7

GND

0.981

0.504

8

3Y

0.981

0.807

9

3A

0.971

1.105

10

3B

0.722

1.115

11

4Y

0.551

1.115

12

4A

0.331

1.115

13

4B

0.132

1.105

14

VCC

0.132

0.65

CONNECT CHIP BACK TO VCC OR FLOAT

Pad Layout and Functions

Logic Diagram

Function Table

INPUTS

OUTPUT

A

B

Y

L

L

H

H

L

H

L

H

H

H

H

L

H = High level (steady state)

L = Low level (steady state)

1300µm (51.18 mils)

0,0

9

8

7

6

5

4

3

2

1

14

13

12

11

10

1A

1B

2A

2B

3A

3B

4A

4B

1

2

4

5

9

10

12

13

3

6

8

11

1Y

2Y

3Y

4Y

Pad 14 = VCC

Pad 7 = GND

 

COORDINATES MARKED IN DIE PASSIVATION FOR ORIENTATION