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GL9714 Datasheet(PDF) 28 Page - GENESYS LOGIC

No. de pieza GL9714
Descripción Electrónicos  PCI ExpressTM PIPE x4 PHY
PDF  46 Pages
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Fabricante Electrónico  GENESYS [GENESYS LOGIC]
Página de inicio  http://www.genesyslogic.com
Logo GENESYS - GENESYS LOGIC

GL9714 Datasheet(HTML) 28 Page - GENESYS LOGIC

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GL9714 PCI Express
TM PIPE x4 PHY
©2004-2007 Genesys Logic Inc. - All rights reserved.
Page 28
5.3 Receiver Data Path Per Lane
Differential Recieiver
Data Recovery Circuit
(DRC)
Serial to Paralle
Elastic Buffer
Loopback path to transmitter
RXN
RXP
RXIDLE
Clock Recovery Circuit
2.5 GHz
K28.5 Detection
RXVLD
RXPLR
Receiver
Status
RXSTS
x10
x10
8b 10b Decoder
x8
Optional 8, 16-bit
Data
x16 or x8
RXDK
Recovered Symbol Clock
Buffer Overflow/Underflow
SKP Added/Removed
Decode Error
Disparity
Error
250 MHz
PCL
Figure 5.3 - Receiver Data Path per Lane



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