GL800HT25 datasheet(14/20 Pages) GENESYS

14 / 20 page

GL800HT25 USB 2.0 UTMI Compliant Transceiver IP Core

Page 14

data for next transfer on the Data bus. If TXVLD is asserted and

TXRDY is negated, the SIE must hold the previously asserted data

on the Data bus. From the time TXVLD is negated, TXRDY is a

don’t care for the SIE.

D0~D15

27~30,

33~40,

43~46

Data bus 0~15

DVDD0

Positive digital supply (3.3V)

DVDD1

Positive digital supply

UMC 0.35um sample : 3.3V

TSMC 0.25um sample : 2.5V

DGND0~1

32,42

Digital ground (0V)

LINEST1

LINEST0

Line State. These signals reflect the current state of the single

ended receivers. They are combinatorial until a “usable” CLK30 is

available then they are synchronized to CLK30. They directly

reflect the current state of the DP (LineState[0]) and DM

(LineState[1]) signals:

DM DP Description

0: SE0

1: ‘J’ State

2: ‘K’ State

3: SE1

Notation:

Type

Output

Input

Bi-directional

B/I

Bi-directional, default input

B/O

Bi-directional, default output

Power / Ground

Analog

Automatic output low when suspend

Internal pull up

Internal pull down

odpu

Open drain with internal pull up

GL800HT25 Datasheet(PDF) 14 Page - GENESYS LOGIC

GL800HT25 Datasheet(HTML) 14 Page - GENESYS LOGIC

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20

Datasheet Descarga

Enlace URL