VIPER50BSP datasheet(16/20 Pages) STMICROELECTRONICS

16 / 20 page

VIPer50B

13V

OSC

COMP

SOURCE

DRAIN

VDD

ISO1

Frominput

diodes bri dge

To seconda

filtering and load

FC005 00

Figure 22: Recommended layout

LAYOUT CONSIDERATIONS

Some simple rules insure a correct running of

switching power supplies. They may be classified

into two categories:

- To minimise power loops: the way the switched

power current must be carefully analysed and

the corresponding paths must present the

smallest inner loop area as possible. This

avoids radiated EMC noises, conducted EMC

noises by magnetic coupling, and provides a

better

efficiency

eliminating

parasitic

inductances, especially on secondary side.

- To use different tracks for low level signals and

power ones. The interferences due to a mixing

of signal and power may result in instabilities

and/or anomalous behaviour of the device in

case

violent

power

surge

(Input

overvoltages, output short circuits...).

In case of VIPer, these rules apply as shown on

figure 22.

The loops C1-T1-U1, C5-D2-T1,

C7-D1-T1 must be minimised. C6 must be as

possible

from

T1.

The

signal

components C2, ISO1, C3 and C4 are using a

dedicated track to be connected directly to the

source of the device.

VIPER50B/BSP

16/20

VIPER50BSP Datasheet(PDF) 16 Page - STMicroelectronics

VIPER50BSP Datasheet(HTML) 16 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20

Datasheet Descarga

Enlace URL