HT45RM03 datasheet(15/54 Pages) HOLTEK

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HT45RM03

Rev. 1.10

February 16, 2007

T 0 M 1

T 0 M 0

T M R 0

T 0 E

T 0 M 1

T 0 M 0

T 0 O N

P u l s e W i d t h

M e a s u r e m e n t

M o d e C o n t r o l

8 - b i t T i m e r / E v e n t C o u n t e r

P r e l o a d R e g i s t e r

8 - b i t T i m e r / E v e n t

C o u n t e r ( T M R 0 )

D a t a B u s

R e l o a d

O v e r f l o w

t o I n t e r r u p t

7 - s t a g e P r e s c a l e r

8 - 1 M U X

f S Y S

f I N T

T 0 P S C 2 ~ T 0 P S C 0

P F D 0

Timer/Event Counter 0

T 1 M 1

T 1 M 0

T M R 1

T 1 E

T 1 M 1

T 1 M 0

T 1 O N

P u l s e W i d t h

M e a s u r e m e n t

M o d e C o n t r o l

8 - b i t T i m e r / E v e n t C o u n t e r

P r e l o a d R e g i s t e r

8 - b i t T i m e r / E v e n t

C o u n t e r ( T M R 1 )

D a t a B u s

R e l o a d

O v e r f l o w

t o I n t e r r u p t

7 - s t a g e P r e s c a l e r

8 - 1 M U X

f S Y S

f I N T

T 1 P S C 2 ~ T 1 P S C 0

P F D 1

Timer/Event Counter 1

Timer/Event Counter

Two timer/event counters (TMR0,TMR1) are imple-

mented in the microcontroller. The Timer/Event Counter

0 and Timer/Event Counter 1 contain 8-bit programmable

count-up counter and the clock may come from an exter-

nal source or an internal clock source.

There are four registers related to the Timer/Event

Counter 0; TMR0 (0DH), TMR0C (0EH), the

Timer/Event Counter 1; TMR1(10H), TMR1C (11H).

Writing TMR0/TMR1 makes the starting value be placed

in the Timer/Event Counter 0/1 preload register and

reading TMR0/1 get the contents of the Timer/Event

Counter 0/1. The TMR0C and TMR1C are Timer/Event

Counter control register 0/1, which defines the operating

mode, counting enable or disable and an active edge.

The T0M0/T1M0 and T0M1/T1M1 bits define the opera-

tion mode. The event count mode is used to count exter-

nal events, which means that the clock source is from an

external (TMR0, TMR1) pin. The timer mode functions

as a normal timer with the clock source coming from the

internal selected clock source. Finally, the pulse width

measurement mode can be used to count the high or

low level duration of the external signal (TMR0, TMR1),

and the counting is based on the internal selected clock

source.

In the event count or timer mode, the Timer/Event Counter

0/1 starts counting at the current contents in the

timer/event counter and ends at FFH. Once an overflow

occurs, the counter is reloaded from the timer/event coun-

ter preload register, and generates an interrupt request

flag (T0F; bit 5 of the INTC1, T1F; bit 6 of the INTC1).

In the pulse width measurement mode with the values of

the T0ON/T1ON and T0E/T1E bits equal to

²1², after the

TMR0/TMR1 has received a transient from low to high

(or high to low if the T0E/T1E bit is

²0²), it will start count-

ing until the TMR0/TMR1 returns to the original level and

resets the T0ON/T1ON.

The measured result remains in the timer/event counter

even if the activated transient occurs again. In other

words, only 1-cycle measurement can be made until the

T0ON/T1ON is set. The cycle measurement will

re-function as long as it receives further transient pulse.

In this operation mode, the timer/event counter begins

counting not according to the logic level but to the tran-

sient edges. In the case of counter overflows, the coun-

ter is reloaded from the timer/event counter register and

issues an interrupt request, as in the other two modes,

i.e., event and timer modes.

To enable the counting operation, the Timer ON bit

(T0ON; bit 4 of the TMR0C or T1ON; bit 4 of the

TMR1C) should be set to

²1². In the pulse width mea-

surement mode, the T0ON/T1ON is automatically

cleared after the measurement cycle is completed. But

in the other two modes, the T0ON/T1ON can only be re-

set by instructions.

The overflow of the Timer/Event Counter 0/1 is one of the

wake-up sources and the Timer/Event Counter 0/1 can

also be applied to a PFD (Programmable Frequency Di-

vider) output at PD0 by software control. Only one PFD

(PFD0 or PFD1) can be applied to PD0 by software. No

P F D S o u r c e O p t i o n

P F D 0

P F D 1

P D 0 D a t a C T R L

P F D

PFD Source Option

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