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PPC440EPX-SPAFFFTS Datasheet(PDF) 6 Page - Applied Micro Circuits Corporation |
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PPC440EPX-SPAFFFTS Datasheet(HTML) 6 Page - Applied Micro Circuits Corporation |
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6 / 94 page ![]() 440EPx – PPC440EPx Embedded Processor Preliminary Data Sheet 6 AMCC Proprietary Revision 1.26 – October 15, 2007 Block Diagram Figure 2. PPC440EPx Functional Block Diagram Processor DCR Bus 32KB On-chip Peripheral Bus (OPB 0) GPIO IIC UART PLB (PLB4—128 bits) DDR2/1 External Peripheral Controller Controller Clock Control, Reset Power Mgmt JTAG Trace Timers MMU - 30-bit addr - 32/16-bit data - 14-bit addr - 64/32-bit data NAND Flash Controller UIC I-Cache 32KB D-Cache PPC440 PCI Bridge x2 x4 MAL Ethernet x2 DCRs GPT ZMII 83MHz max 10/100/1000 66MHz max 333MHz max PLB (PLB3—64 bits) PLB-PLB Bridges SPI USB 2.0 - 32 bits - 6 devices FPU External DMA Controller OPB Bridge BSC 10 DMA Controller OPB Bridge 2.0 PHY D+/D − OPB 1 Interrupts Security SRAM 16KB Device Host (optional) data rate RGMII OPB 2 SDRAM OPB Bridge OPB Bridge The PPC440EPx is a system on a chip (SOC) using IBM CoreConnect Bus™ Architecture. Address Maps The PPC440EPx incorporates two address maps. The first is a fixed processor System Memory Address Map. This address map defines the possible contents of various address regions which the processor can access. The second is the DCR Address Map for Device Configuration Registers (DCRs). The DCRs are accessed by software running on the PPC440EPx processor through the use of mtdcr and mfdcr instructions. |
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