FM25640 datasheet(8/13 Pages) RAMTRON

8 / 13 page

FM25640 - Automotive Temp.

Rev. 3.0

July 2007

8 of 13

345

op-code

MSB

13-bit Address

121110

LSB MSB

LSB

SCK

Data

Figure 9. Memory Write

34567

567

34567

op-code

MSB

13-bit Address

12 11 10

210

54321

LSB MSB

LSB

SCK

Data

Figure 10. Memory Read

Endurance

Internally, a FRAM operates with a read and restore

mechanism

similar

DRAM.

Therefore,

endurance cycles are applied for each access: read or

write. The FRAM architecture is based on an array of

rows and columns. Each access causes a cycle for an

entire row. Therefore, data locations targeted for

substantially differing numbers of cycles should not

be located within the same row. In the FM25640,

there are 2048 rows each 32 bits wide. Each 4 bytes

in the address mark the beginning of a new row.

Regardless, FRAM read and write endurance is

effectively unlimited at the 4 MHz clock speed.

Even at 2000 accesses per second to the same row, 15

years time will pass before 10

12 endurance cycles

occur.

FM25640 Datasheet(PDF) 8 Page - Ramtron International Corporation

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