HD66789 datasheet(9/156 Pages) RENESAS

9 / 156 page

HD66789

Preliminary

Rev.0.12, May 09 2003, page 9 of 156

Signals

Number

of Pins

I/O

Connected

Functions

MPU

Select register.

Low: Index/status, High: Control

Fix to the “IOVcc” or “GND” level while using SPI.

WR*/SCL

MPU

In 80-system bus interface mode, serves as a write strobe signal.

Data are written at “Low” level.

In Serial Peripheral Interface mode, serves as synchronizing

clock signal.

RD*

MPU

In 80-system bus interface mode, serves as read-strobe signal.

Data are read at the low level of the signal.

Fix to the “IOVcc” or “GND” level while using SPI.

DB0/SDI

I/O

MPU

18-bit parallel bi-directional data bus.

8-bit bus: DB17-DB10

9-bit bus: DB17-DB9

16-bit bus: DB17-DB10 and DB8-DB1

18-bit bus: DB17-DB0

Unused pins must be fixed to the IOVcc or GND level.

Serves as serial data input pin (SDI) in Serial Peripheral

Interface mode, where data are input on the rising edge of SCL

signal.

DB1/SDO

I/O

MPU

18-bit parallel bi-directional data bus.

8-bit bus: DB17-DB10

9-bit bus: DB17-DB9

16-bit bus: DB17-DB10 and DB8-DB1

18-bit bus: DB17-DB0

Unused pins must be fixed to the IOVcc or GND level.

Serves as serial data output pin (SDO) in Serial Peripheral

Interface mode, where data are output on the falling edge of the

SCL signal.

DB2~DB17

I/O

MPU

18-bit parallel bi-directional data bus.

8-bit bus: DB17-DB10

9-bit bus: DB17-DB9

16-bit bus: DB17-DB10 and DB8-DB1

18-bit bus: DB17-DB0

Unused pins must be fixed to the IOVcc or GND level.

ENABLE

MPU

Indicate whether RAM data are valid or not when RGB interface

is used.

Low: Selected (access enabled)

High: Not selected (access disabled)

Must be fixed to the IOVcc or GND level when not used.

ENABLE signal invert the polarity according to the setting of EPL

resister.

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