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ST72324BK Datasheet(PDF) 51 Page - STMicroelectronics

No. de pieza ST72324BK
Descripción Electrónicos  8-bit MCU, 3.8 to 5.5 V operating range with 8 to 32 Kbyte Flash/ROM, 10-bit ADC, 4 timers, SPI, SCI
PDF  188 Pages
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Fabricante Electrónico  STMICROELECTRONICS [STMicroelectronics]
Página de inicio  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

ST72324BK Datasheet(HTML) 51 Page - STMicroelectronics

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ST72324B
Power saving modes
51/188
Figure 28.
HALT timing overview
Figure 29.
Halt mode flowchart
1.
WDGHALT is an option bit. See Section 14.1 on page 172 for more details.
2.
Peripheral clocked with an external clock source can still be active.
3.
Only some specific interrupts can exit the MCU from Halt mode (such as external interrupt). Refer to
Table 24: Interrupt mapping for more details.
4.
Before servicing an interrupt, the CC register is pushed on the stack. The I[1:0] bits of the CC register are
set to the current software priority level of the interrupt routine and recovered when the CC register is
popped.
Halt
Run
Run
256 or 4096 CPU
cycle delay
Reset
or
interrupt
Halt
instruction
Fetch
vector
[MCCSR.OIE = 0]
Halt instruction
Reset
Interrupt(3)
Y
N
N
Y
CPU
Oscillator
Peripherals(2)
I[1:0] bits
off
off
10
off
Fetch reset vector
or service interrupt
CPU
Oscillator
Peripherals
I[1:0] bits
on
off
XX(4)
on
CPU
Oscillator
Peripherals
I[1:0] bits
on
on
XX(4)
on
256 or 4096 CPU clock
delay
Watchdog
Enable
Disable
WDGHALT(1)
0
Watchdog
reset
1
(MCCSR.OIE = 0)
cycle



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