5.5 Thermal Information

THERMAL METRIC (1)

ESD701

UNIT

DPY (X1SON)

2 PINS

RθJA

Junction-to-ambient thermal resistance

262.6

°C/W

RθJC(top)

Junction-to-case (top) thermal resistance

132.3

°C/W

RθJB

Junction-to-board thermal resistance

78.5

°C/W

ΨJT

Junction-to-top characterization parameter

2.2

°C/W

ΨJB

Junction-to-board characterization parameter

78.0

°C/W

RθJC(bot)

Junction-to-case (bottom) thermal resistance

NA

°C/W

(1)

For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

5.6 Electrical Characteristics

At TA = 25°C unless otherwise noted

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

VRWM

Reverse stand-off voltage

IIO < 10 nA

-24

24

V

ILEAK

Leakage current at VRWM

VIO = ±24 V, I/O to GND

2

10

nA

VBR

Breakdown voltage, I/O to GND (1)

IIO = ±10 mA

25.5

35.5

V

VHOLD

Holding voltage (2)

TLP, IO to GND or GND to IO

31

VCLAMP

Surge clamping voltage, tp = 8/20 µs

(3)

IPP = 3 A, I/O to GND

37

V

VCLAMP

Surge clamping voltage, tp = 8/20 µs

(3)

IPP = 3 A, GND to I/O

37

V

VCLAMP

TLP clamping voltage, tp = 100 ns (4)

IPP = 16 A (100 ns TLP), I/O to GND

41

V

VCLAMP

TLP clamping voltage, tp = 100 ns (4)

IPP = 16 A (100 ns TLP), GND to I/O

41

V

RDYN

Dynamic resistance (5)

I/O to GND

0.84

Ω

GND to I/O

0.84

CLINE

Line capacitance, IO to GND

VIO = 0 V, f = 1 MHz

0.3

0.5

pF

(1)

VBR is defined as the voltage obtained at 1 mA when sweeping the voltage up, before the device latches into the snapback state

(2)

VHOLD is defined as the voltage when 1 mA is applied, after the device has successfully latched into the snapback state.

(3)

Device stressed with 8/20 µs exponential decay waveform according to IEC 61000-4-5

(4)

Non-repetitive square wave current pulse, Transmission Line Pulse (TLP); ANSI / ESD STM5.5.1-2008

(5)

Extraction of RDYN using least squares fit of TLP characteristics between I = 10 A and I = 20 A

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ESD701

SLVSI66 – OCTOBER 2024

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