SC16C852LIB datasheet(21/60 Pages) PHILIPS

21 / 60 page

SC16C852L_2

Product data sheet

Rev. 02 — 25 January 2007

21 of 60

NXP Semiconductors

SC16C852L

1.8 V dual UART with 128-byte FIFOs and IrDA encoder/decoder

6.14.3.2

Auto address detection

If Special Character Detect is enabled (EFR[5] is set and the Xoff2 register contains the

address byte) the receiver will try to detect an address byte that matches the programmed

character in the Xoff2 register. If the received byte is a data byte or an address byte that

does not match the programmed character in the Xoff2 register, the receiver will discard

these data. Upon receiving an address byte that matches the Xoff2 character, the receiver

will be automatically enabled if not already enabled, and the address character is pushed

into the RX FIFO along with the parity bit (in place of the parity error bit). The receiver also

generates a line status interrupt (IER[2] must be set to ‘1’ at this time). The receiver will

then receive the subsequent data from the ‘master’ station until being disabled by the

controller after having received a message from the ‘master’ station.

If another address byte is received and this address byte does not match the Xoff2

character, the receiver will be automatically disabled and the address byte is ignored. If

the address byte matches the Xoff2 character, the receiver will put this byte in the RX

FIFO along with the parity bit in the parity error bit (LSR bit 2).

Table 10 details the assigned bit functions for the SC16C852L internal registers. The

assigned bit functions are more fully deﬁned in Section 7.1 through Section 7.23.

SC16C852LIB Datasheet(PDF) 21 Page - NXP Semiconductors