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PM8621 Datasheet(PDF) 71 Page - PMC-Sierra, Inc |
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PM8621 Datasheet(HTML) 71 Page - PMC-Sierra, Inc |
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71 / 184 page ![]() NSE-8G™ Standard Product Data Sheet Preliminary Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use 70 Document ID: PMC-2010850, Issue 1 Register 00BH: NSE-8G Interrupt Enable Register Bit Type Function Default Bit 31:1 R Unused X Bit 0 R/W INTE 0 This register allows the CPU to disable or enable NSE-8G interrupts with a single write. INTE This bit, when ‘1’, enables the INTB pin on the NSE. When set to ‘0’ INTB is held ‘1’. |
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