MPC905

TIMING SOLUTIONS

DL207 — Rev 0

5

MOTOROLA

shows a step in the waveform, this step is caused by the

impedance mismatch seen looking into the driver. The

parallel combination of the 40

Ω series resistor plus the output

impedance does not match the parallel combination of the

line impedances. The voltage wave launched down the two

lines will equal:

VL = VS ( Zo / Rs + Ro +Zo) = 3.0 (25/55) = 1.36V

At the load end the voltage will double, due to the near

unity reflection coefficient, to 2.73V. It will then increment

towards the quiescent 3.0V in steps separated by one round

trip delay (in this case 4.0ns).

Figure 5. Single versus Dual Waveforms

TIME (nS)

3.0

2.5

2.0

1.5

1.0

0.5

0

2

4

6

8

10

12

14

OutB

tD = 3.9386

OutA

tD = 3.8956

In

Since this step is well above the threshold region it will not

cause any false clock triggering, however designers may be

uncomfortable with unwanted reflections on the line. To

better match the impedances when driving multiple lines the

situation in Figure 6 should be used. In this case the series

terminating resistors are reduced such that when the parallel

combination is added to the output buffer impedance the line

impedance is perfectly matched.

Figure 6. Optimized Dual Line Termination

10

Ω

MPC905

OUTPUT

BUFFER

RS = 30Ω

ZO = 50Ω

RS = 30Ω

ZO = 50Ω

10

Ω + 30Ω k 30Ω = 50Ω k 50Ω

25

Ω = 25Ω

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

MPC905

1:6 PCI Clock Generator/Fanout Buffer

NETCOM

IDT™ 1:6 PCI Clock Generator/Fanout Buffer

Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc

MPC905

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