P4C189

Page 5 of 8

Document # SRAM100 Rev OR

Notes:

9. CS and WE must be LOW for WRITE cycle.

10. If CS goes HIGH simultaneously with WE high, the output remains

in a high impedance state.

TIMING WAVEFORM OF WRITE CYCLE NO. 2 (CS

CS

CS

CS

11. Write Cycle Time is measured from the last valid address to the first

transition address.