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CS8416-CSZ Datasheet(PDF) 55 Page - Cirrus Logic |
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CS8416-CSZ Datasheet(HTML) 55 Page - Cirrus Logic |
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55 / 60 page ![]() DS578F3 55 CS8416 18.2.5 Jitter Attenuation Shown in Figure 25 is the jitter attenuation plot. The AES3 and IEC60958-4 specifications state a maxi- mum of 2 dB jitter gain or peaking. 10 1 10 0 10 1 10 2 10 3 10 4 10 5 12 10 8 6 4 2 0 2 4 J itter F requency (Hz) Figure 25. Jitter Attenuation Characteristics of PLL |
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