DS687F1

17

CS5343/4

4.6

Synchronization of Multiple Devices

In systems where multiple ADCs are required, care must be taken to achieve simultaneous sampling. To

ensure synchronous sampling, the MCLK, SCLK, and LRCK signals must be the same for all of the CS5343

and CS5344 devices in the system.

5. FILTER PLOTS

Figure 8. Single-Speed Mode Stopband Rejection

Figure 9. Single-Speed Mode Transition Band

-140

-130

-120

-110

-100

-90

-80

-70

-60

-50

-40

-30

-20

-10

0

0.0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1.0

Frequency (norm alized to Fs)

-140

-130

-120

-110

-100

-90

-80

-70

-60

-50

-40

-30

-20

-10

0

0.40

0.42

0.44

0.46

0.48

0.50

0.52

0.54

0.56

0.58

0.60

Frequency (norm alized to Fs)

Figure 10. Single-Speed Mode Transition Band (Detail)

Figure 11. Single-Speed Mode Passband Ripple

-0.10

-0.08

-0.06

-0.04

-0.02

0.00

0.02

0.04

0.06

0.08

0.10

0.00

0.05

0.10

0.15

0.20

0.25

0.30

0.35 0.40

0.45

0.50

Frequency (norm alized to Fs)

-10

-9

-8

-7

-6

-5

-4

-3

-2

-1

0

0.46

0.47

0.48

0.49

0.50

0.51

0.52

Frequency (norm alized to Fs)