DS613F1

9

CS4344/5/6/8

SWITCHING CHARACTERISTICS - SERIAL AUDIO INTERFACE

11. Not all sample rates are supported for all clock ratios. See Table 1, “Common Clock Frequencies,” on

page 12 for supported ratio’s and frequencies.

12. In Internal SCLK Mode, the Duty Cycle must be 50%

+/− 1/2 MCLK Period.

13. The SCLK / LRCK ratio may be either 32, 48, 64, or 72. This ratio depends on part type and

MCLK/LRCK ratio. (See Figures 7-9)

Parameters

Symbol

Min

Typ

Max

Units

MCLK Frequency

0.512

-

50

MHz

MCLK Duty Cycle

45

-

55

%

Input Sample Rate

All MCLK/LRCK ratios combined

(Note 11)

256x, 384x, 1024x

256x, 384x

512x, 768x

1152x

128x, 192x

64x, 96x

128x, 192x

Fs

2

2

84

42

30

50

100

168

200

50

134

67

34

100

200

200

kHz

kHz

kHz

kHz

kHz

kHz

kHz

kHz

External SCLK Mode

LRCK Duty Cycle (External SCLK only)

45

50

55

%

SCLK Pulse Width Low

20

-

-

ns

SCLK Pulse Width High

20

-

-

ns

SCLK Duty Cycle

45

50

55

%

SCLK rising to LRCK edge delay

20

-

-

ns

SCLK rising to LRCK edge setup time

20

-

-

ns

SDIN valid to SCLK rising setup time

20

-

-

ns

SCLK rising to SDIN hold time

20

-

-

ns

Internal SCLK Mode

LRCK Duty Cycle (Internal SCLK only)

(Note 12)

-50

-

%

SCLK Period

(Note 13)

--

ns

SCLK rising to LRCK edge

--

µs

SDIN valid to SCLK rising setup time

--

ns

SCLK rising to SDIN hold time

MCLK / LRCK =1152, 1024, 512, 256, 128, or 64

--

ns

SCLK rising to SDIN hold time

MCLK / LRCK = 768, 384, 192, or 96

--

ns

SCLK

----------------

tsclkw

2

------------------

512

(

)Fs

----------------------10

+

512

(

)Fs

----------------------15

+

384

(

)Fs

----------------------15

+