LTM4657 datasheet(11/32 Pages) AD

11 / 32 page

LTM4703

Rev. 0

For more information www.analog.com

PIN FUNCTIONS

SVIN (Pin A4): Signal VIN. This pin supplies current to the

LTM4703 internal circuitry and regulator. If connected to

a different supply other than VIN, place a 1µF local bypass

capacitor on this pin.

VOUT (Banks 1 and 2): Power Output Pins. Apply an

output load between these pins and the GND pins.

Recommend placing an output decoupling capacitor

directly between these pins and the GND pins.

GND (Bank 3 and Pin G7): Power Ground Pins for Both

Input and Output Returns.

VIN (Bank 4): Power Input Pins. Apply input voltage

between these pins and the GND pins. Recommend plac-

ing an input decoupling capacitor directly between the VIN

pins and the GND pins.

TSENSE+ (Pin B1): High-Side of the Internal Temperature

Monitor Pin. An internal diode-connected NPN transistor

is placed between the TSENSE+ and TSENSE– pins. See the

Applications Information section.

TSENSE– (Pin B2): Low-Side of the Internal Temperature

Monitor Pin.

RUN (Pin C1): Run Control Input. Enables chip operation

by connecting RUN above 1.32V (typical). Connecting it

below 0.4V shuts down the part.

COMPa (Pin C2): Output of the Internal Error Amplifier.

The voltage on this pin controls the peak switch current.

Connect the COMPa pins from different channels together

for parallel operation. Connect to COMPb to use the inter-

nal compensation. Or connect to an external RC network

to use customized compensation.

COMPb (Pin C3): Internal Compensation Network.

Connect to COMPa to use the internal compensation in

the majority of applications.

RT (Pin D1): This pin sets the oscillator frequency with

an external resistor to AGND.

AGND (Pin D2): Analog Ground. Ground return for

SYNC, RT, and COMP pins. The AGND and GND pins are

internally connected.

INTVCC (Pin D3): Internal 3.4V Regulator Bypass Pin. The

internal power drivers and control circuits are powered

by this voltage. Do not load the INTVCC pin with external

circuitry. This pin should be floated.

SET (Pin E1): Output Voltage Set. This pin is the non-

inverting input of the error amplifier and the regulation

set-point for the LTM4703. The SET pin sources a preci-

sion 100µA current that flows through an external resistor

connected between SET and GND. The LTM4703’s output

voltage is determined by VSET = ISET • RSET. The output

voltage range is from 0.3V to 6V. Adding a capacitor from

SET to GND improves noise at the expense of increased

start-up time. For optimum load regulation, Kelvin con-

nects the ground side of the SET pin resistor directly to

the load.

PGSET (Pin E2): Power Good Set. The PG pin pulls low

if PGSET increases above 540mV or decreases below

465mV. Connecting a pull-up resistor between VOUT and

PGSET sets the programmable power good threshold

with Equation 1.

RPGSET = (2 • VOUT – 1) • 49.9k

(1)

As discussed in the Applications Information section,

PGSET also activates the fast start-up circuitry. If the

power is good and the fast start-up functionalities are not

needed, the PGSET pin must be connected to an external

0.5V. Do not float the PGSET pin.

PHMODE (Pin E3): The PHMODE pin sets the phase shift

of the clock signal of the CLKOUT pin. Connect PHMODE

to ground for a 180° phase shift, float for a 120° phase

shift, and connect high to INTVCC (~3.4V) or an external

supply >3V for a 90° phase shift.

VOSNS (Pin F1): Output Voltage Sense. This pin is the

inverting input to the error amplifier. For optimal transient

performance and load regulation, Kelvin connects VOSNS

directly to the output capacitor and the load. Also, connect

the GND connections of the output capacitor and the SET

pin capacitor directly together.

PACKAGE ROW AND COLUMN LABELING MAY VARY

AMONG µModule PRODUCTS. REVIEW EACH PACKAGE

LAYOUT CAREFULLY.

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