AD9913

Data Sheet

Rev. E | Page 2 of 32

TABLE OF CONTENTS

Features .............................................................................................. 1

 

Applications ...................................................................................... 1

 

General Description ......................................................................... 1

 

Functional Block Diagram .............................................................. 1

 

Revision History ............................................................................... 2

 

Specifications .................................................................................... 3

 

Electrical Specifications ............................................................... 3

 

Absolute Maximum Ratings ........................................................... 5

 

ESD Caution.................................................................................. 5

 

Equivalent Circuits....................................................................... 5

 

Pin Configuration and Function Descriptions ............................ 6

 

Typical Performance Characteristics............................................. 8

 

Applications Circuits ..................................................................... 11

 

Theory of Operation ...................................................................... 12

 

DDS Core .................................................................................... 12

 

Auxiliary Accumulator.............................................................. 13

 

10-Bit DAC.................................................................................. 13

 

I/O Port........................................................................................ 13

 

Profile Selections ........................................................................ 13

 

Modes of Operation ....................................................................... 14

 

Single Tone Mode ...................................................................... 14

 

Direct Switch Mode ................................................................... 14

 

Programmable Modulus Mode ................................................ 14

 

Linear Sweep Mode.................................................................... 14

 

Clock Input (REF_CLK) ............................................................... 18

 

REF_CLK Overview................................................................... 18

 

Crystal-Driven REF_CLK ......................................................... 18

 

Direct-Driven REF_CLK .......................................................... 18

 

CMOS-Driven REF_CLK ......................................................... 18

 

Phase-Locked Loop (PLL) Multiplier ..................................... 18

 

PLL Lock Indication .................................................................. 19

 

Power-Down Features............................................................... 21

 

I/O Programming........................................................................... 22

 

Serial Programming................................................................... 22

 

Parallel I/O Programming ........................................................ 23

 

Register Update (I/O Update) .................................................. 25

 

Register Map and Bit Descriptions .............................................. 26

 

Register Map ............................................................................... 26

 

Register Bit Descriptions........................................................... 28

 

Outline Dimensions....................................................................... 32

 

Ordering Guide .......................................................................... 32

 

REVISION HISTORY

11/2020—Rev. D to Rev. E

Changed CP-32-2 to CP-32-7......................................Throughout

Changes to Figure 3.......................................................................... 6

Updated Outline Dimensions....................................................... 32

Changes to Ordering Guide.......................................................... 32

3/2019—Rev. C to Rev. D

Change to DAC Control Register (0x02), Table 9..................... 26

Updated Outline Dimensions....................................................... 32

11/2017—Rev. B to Rev. C

Changed CP-32-7 to CP-32-2......................................Throughout

Updated Outline Dimensions....................................................... 32

Changes to Ordering Guide.......................................................... 32

8/2016—Rev. A to Rev. B

Changes to Table 7 ......................................................................... 20

Updated Outline Dimensions....................................................... 32

Changes to Ordering Guide.......................................................... 32

6/2010—Rev. 0 to Rev. A

Added Digital Input Voltage to Table 2.........................................5

Added Exposed Pad Notation to Figure 3 and Table 3 ...............5

Changes to Programmable Modulus Mode Section ................. 14

Changes to Serial Programming Section .................................... 22

Changes to Data Write Operation Section ................................. 24

Added Register Update (I/O Update) section and Figure 35 .. 25

Added Endnote 1 to Table 9 ......................................................... 26

Changes to Register Bit Descriptions Section and Bit 7

Description in Table 10 ................................................................. 28

Changes to Table 15 and Table 16 ............................................... 31

Added Exposed Pad Notation to Outline Dimensions............. 32

10/2007—Revision 0: Initial Version