Motor de Búsqueda de Datasheet de Componentes Electrónicos
  Spanish  ▼
ALLDATASHEET.ES

X  

MSC7119 Datasheet(PDF) 30 Page - Freescale Semiconductor, Inc

No. de pieza MSC7119
Descripción Electrónicos  Low-Cost 16-bit DSP with DDR Controller and 10/100 Mbps Ethernet MAC
PDF  56 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Fabricante Electrónico  FREESCALE [Freescale Semiconductor, Inc]
Página de inicio  http://www.freescale.com
Logo FREESCALE - Freescale Semiconductor, Inc

MSC7119 Datasheet(HTML) 30 Page - Freescale Semiconductor, Inc

Back Button MSC7119 Datasheet HTML 26Page - Freescale Semiconductor, Inc MSC7119 Datasheet HTML 27Page - Freescale Semiconductor, Inc MSC7119 Datasheet HTML 28Page - Freescale Semiconductor, Inc MSC7119 Datasheet HTML 29Page - Freescale Semiconductor, Inc MSC7119 Datasheet HTML 30Page - Freescale Semiconductor, Inc MSC7119 Datasheet HTML 31Page - Freescale Semiconductor, Inc MSC7119 Datasheet HTML 32Page - Freescale Semiconductor, Inc MSC7119 Datasheet HTML 33Page - Freescale Semiconductor, Inc MSC7119 Datasheet HTML 34Page - Freescale Semiconductor, Inc Next Button
Zoom Inzoom in Zoom Outzoom out
 30 / 56 page
background image
MSC7119 10/100 Mbps Ethernet MAC Data Sheet, Rev. 6
Electrical Characteristics
Freescale Semiconductor
30
2.5.6.2
Transmit Signal Timing
2.5.6.3
Asynchronous Input Signal Timing
Table 22. Transmit Signal Timing
No.
Characteristics
Min
Max
Unit
800
Transmit clock period:
• MII: TXCLK
• RMII: REFCLK
40
20
ns
ns
801
Transmit clock pulse width high—as a percent of clock period
• MII: RXCLK
• RMII: REFCLK
35
14
7
65
%
ns
ns
802
Transmit clock pulse width low—as a percent of clock period:
• MII: RXCLK
• RMII: REFCLK
35
14
7
65
%
ns
ns
805
Transmit clock to TXDn, TX_EN, TX_ER invalid
4
ns
806
Transmit clock to TXDn, TX_EN, TX_ER valid
14
ns
Figure 11. Ethernet Receive Signal Timing
Table 23. Asynchronous Input Signal Timing
No.
Characteristics
Min
Max
Unit
807
• MII: CRS and COL minimum pulse width (1.5
× TXCLK period)
• RMII: CRS_DV minimum pulse width (1.5 x REFCLK period)
60
30
ns
ns
Figure 12. Asynchronous Input Signal Timing
Valid
Transmit
TX_EN
TXDn
TX_ER
805
806
clock
800
801
802
CRS
COL
807
CRS_DV



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56


Datasheet Descarga

Go To PDF Page


Enlace URL



¿ALLDATASHEET es útil para Ud.?  [ DONATE ] 

Todo acerca de Alldatasheet   |   Publicidad   |   Contáctenos   |   Política de Privacidad   |   Enlace a la hoja de datos    |   Intercambio de Enlaces   |   Lista de Fabricantes
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com