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MSC7119 Datasheet(PDF) 30 Page - Freescale Semiconductor, Inc |
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MSC7119 Datasheet(HTML) 30 Page - Freescale Semiconductor, Inc |
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30 / 56 page ![]() MSC7119 10/100 Mbps Ethernet MAC Data Sheet, Rev. 6 Electrical Characteristics Freescale Semiconductor 30 2.5.6.2 Transmit Signal Timing 2.5.6.3 Asynchronous Input Signal Timing Table 22. Transmit Signal Timing No. Characteristics Min Max Unit 800 Transmit clock period: • MII: TXCLK • RMII: REFCLK 40 20 — — ns ns 801 Transmit clock pulse width high—as a percent of clock period • MII: RXCLK • RMII: REFCLK 35 14 7 65 — — % ns ns 802 Transmit clock pulse width low—as a percent of clock period: • MII: RXCLK • RMII: REFCLK 35 14 7 65 — — % ns ns 805 Transmit clock to TXDn, TX_EN, TX_ER invalid 4 — ns 806 Transmit clock to TXDn, TX_EN, TX_ER valid — 14 ns Figure 11. Ethernet Receive Signal Timing Table 23. Asynchronous Input Signal Timing No. Characteristics Min Max Unit 807 • MII: CRS and COL minimum pulse width (1.5 × TXCLK period) • RMII: CRS_DV minimum pulse width (1.5 x REFCLK period) 60 30 — — ns ns Figure 12. Asynchronous Input Signal Timing Valid Transmit TX_EN TXDn TX_ER 805 806 clock 800 801 802 CRS COL 807 CRS_DV |
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