© 2005 Microchip Technology Inc.

DS21127F-page 3

24LCS21

TABLE 1-2:

AC CHARACTERISTICS

Parameter

Symbol

Units

Remarks

Min

Max

Min

Max

Clock frequency

0100

0

400

kHz

Clock high time

4000

—

600

—

ns

Clock low time

4700

—

1300

—

ns

SDA and SCL rise time

—

1000

—

300

ns

(Note 1)

SDA and SCL fall time

—

300

—

300

ns

(Note 1)

Start condition hold time

4000

—

600

—

ns

After this period the first

clock pulse is generated

Start condition setup time

4700

—

600

—

ns

Only relevant for repeated

Start condition

Data input hold time

0—

0

—

ns

(Note 2)

Data input setup time

250

—

100

—

ns

Stop condition setup time

4000

—

600

—

ns

Output valid from clock

—

3500

—

900

ns

(Note 2)

Bus free time

4700

—

1300

—

ns

Time the bus must be free

before a new transmission

can start

—

250

20 + 0.1

250

ns

≤ 100 pF

Input filter spike suppression

(SDA and SCL pins)

—100

—

50

ns

(Note 3)

Write cycle time

—

10

—

10

ms

Byte or Page mode

Transmit-Only Mode Parameters

—

2000

—

1000

ns

4000

—

600

—

ns

4700

—

1300

—

ns

0—

0

—

ns

4000

—

600

—

ns

Mode transition time

—

500

—

500

ns

Transmit-only power-up time

0—

0

—

ns

Input filter spike suppression

—

100

—

100

ns

Endurance

—

1M

—

1M

—

cycles

mode (Note 4)

Note 1:

2:

As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region

(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions.

3:

4:

This parameter is not tested but ensured by characterization. For endurance estimates in a specific

at www.microchip.com.