TPS1663_V03 datasheet(18/46 Pages) TI1

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VIN

VOUT

PGOOD

IIN

CdVdT = Open

COUT = 15 mF

RILIM = 4.02 kΩ

Figure 9-2. Thermal Regulation Loop Response During Power Up With Large Capacitive Load

9.3.2 Undervoltage Lockout (UVLO)

The TPS1663x devices feature an accurate ± 2% adjustable undervoltage lockout functionality. When the

voltage at UVLO pin falls below V(UVLOF) during input undervoltage fault, the internal FET quickly turns off and

FLT is asserted. The UVLO comparator has a hysteresis of 78 mV (typical). To set the input UVLO threshold,

connect a resistor divider network from IN supply to UVLO terminal to GND as shown in Figure 9-3. If the

Undervoltage Lockout function is not needed, the UVLO terminal must be connected to the IN terminal. UVLO

terminal must not be left floating.

UVLO

OVP

V(IN)

UVLOb

OVP

1.2 V

1.12 V

1.2 V

1.12 V

GND

P_IN

Figure 9-3. UVLO and OVP Thresholds Set by R1 , R2 and R3

9.3.3 Overvoltage Protection (OVP)

The TPS1663x incorporate circuitry to protect the system during overvoltage conditions. The TPS16630 features

an accurate ± 2% adjustable overvoltage cut off functionality. A voltage more than V(OVPR) on OVP pin turns off

the internal FET and protects the downstream load. To program the OVP threshold externally, connect a resistor

divider from IN supply to OVP terminal to GND as shown in Figure 9-3. The TPS16632 features an internally

fixed 39-V maximum overvoltage clamp V(OVC) functionality. The TPS16632 clamps the output voltage to V(OVC),

when the input voltage exceeds 40 V. During the output voltage clamp operation, the power dissipation in the

internal MOSFET is PD = (V(IN) – V(OVC)) × I(OUT). Excess power dissipation for a prolonged period can increase

TPS1663

SLVSET9F – SEPTEMBER 2018 – REVISED FEBRUARY 2023

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TPS1663 Datasheet(PDF) 18 Page - Texas Instruments