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PR31500ABC Datasheet(PDF) 22 Page - NXP Semiconductors |
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PR31500ABC Datasheet(HTML) 22 Page - NXP Semiconductors |
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22 / 24 page ![]() Philips Semiconductors Preliminary specification MIPS PR31500 Poseidon embedded processor 1996 Sep 24 22 POWER Tamb = 0 to +70°C, VDD = 3.3 ± 0.3V, External Capacitance = 40pF ITEM PARAMETER RISING/FALLING LIMITS UNIT ITEM PARAMETER RISING/FALLING MIN MAX UNIT 1 VSTANDBY to /PON Rising – 50 – ns 2 VSTANDBY to ONBUTN delay time – 2 – s POWER TIMING DIAGRAM VSTANDBY ONBUTN /PON 1 2 SN00181 Figure 14. CPU RESET Tamb = 0 to +70°C, VDD = 3.3 ± 0.3V, External Capacitance = 40pF ITEM PARAMETER RISING/FALLING LIMITS UNIT ITEM PARAMETER RISING/FALLING MIN MAX UNIT 1 /CPURES low time – 10 – ns /CPURES 1 SN00182 Figure 15. |
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